Over the past several years we’ve seen multiple companies tackle the problem of finding a new memory standard to
replace NAND flash.
Despite NAND’s superior performance characteristics, it faces long-term
scaling issues. One of the technologies that’s bidding fair to take
over the eventual performance crown is phase change memory — and Western
Digital’s HGST subsidiary is ready to demonstrate just how much
performance PCM can offer compared to NAND flash.
This week at the
Flash Memory Summit, HGST will show a prototype SSD designed with phase
change memory that it claims can hit three
million random read I/Os (512-byte) and a random read access latency of 1.5 microseconds.
So, um, how fast is that, really?
Obviously this is the kind of marketing figure that PR departments like to spin,
but even allowing for that, it’s damned fast. Typical random access
read latency for consumer NAND is 0.1ms, or roughly 100 microseconds.
HGST is claiming access latencies almost two orders of magnitude smaller
than the fastest SLC NAND flash you can buy.
The accesses are so fast, in
point of fact, that HGST had to rearchitect the entire PCI Express bus
to stress test the phase change memory. The company has published an
eight-page whitepaper detailing its efforts
— essentially it started with the Non Volatile Memory Express (NVMe)
protocol, then rearchitected it to strip out all unnecessary
communication. According to HGST, strict performance criteria that
actually leverage real-world test scenarios show NAND flash topping out
at roughly 13,000 IOPS rather than the 90,000+ typically claimed by
high-end hardware. The company claims this is limited by roughly 70
microseconds of read latency.
By rearchitecting the bus protocol
into what HGST calls DC Express, it was able to boost performance from
13,000 IOPS to 700,000 IOPS on the same material. From the report: “We
proceeded to slim down the read-side protocol by eliminating unnecessary
packet exchanges over PCI Express and by avoiding mode and context
switching. In this manner we were able to reduce the average round-trip
protocol latency to just over 1 [microsecond], a tenfold improvement
over our current implementation of NVMe-compliance interface protocol.”
Call this one a two-fer — in
addition to demonstrating phase change memory in a small-scale device,
HGST has redefined the storage protocol you’d need to use to operate it
at peak efficiency.
The long road from proof-of-concept to shipping product
The
good news is, these types of demonstrations are absolutely essential to
the long-term goal of shipping product based on PCM. The bad news is
that we’re still years from commercialization. Just like the IBM demonstration of earlier this year,
the HGST hardware was based on Micron phase change memory — and Micron
is taking a strategic break from that business segment. Right now, PCM
is projected to hit the market in 2016 — but it won’t go head-to-head
with NAND in most deployments.
This image is from IBM’s
latest research, but it illustrates the point of where we’ll see PCM
show up first. With write latencies that are merely competitive with
NAND flash, the focus will be on read accesses, where PCM can offer
performance that’s within several orders of magnitude of main memory.
The trick will be designing workloads that fit the “read often, write
rarely” characteristics. [Read: WD releases 6TB Ultrastar He6: The world’s first helium-filled hard drive.]
If
phase change memory starts ramping up for enterprise workloads by 2016,
it’s not ridiculous to think we’d see the consumer equivalent by
2019-2020. A year ago, I thought ReRAM
was the odds-on favorite for an eventual NAND replacement, but I’ve got
to say that the recent advances in phase change memory have me
wondering if its not the better candidate. 100x better read performance
and equivalent write performance is unquestionably good enough to carve
its own niche, assuming issues of yield and density can be ironed out.
Extremetech.com
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