Wednesday 10 February 2016

An end to scaling: Intel’s next-generation chips will sacrifice speed to reduce power


Faster, cheaper, smaller. For decades, those three words drove innovation in Silicon Valley and across the world. Even after clock speed increases flatlined after 2005, the semiconductor industry found ways to drive performance forward while increasing total transistor counts and improving on-die integration of various components. The rise of SoCs, GPGPU, and Intel’s own Xeon Phi are all designed to increase performance even if clock speeds are largely static.
Now, Intel has acknowledged that the future of semiconductors may rely on technologies that reduce absolute performance in exchange for improved power consumption. William Holt, head of Intel’s Technology and Manufacturing Group, made the announcement at the International Solid State Circuits Conference (ISSCC) this past week, when discussing some of the options Intel is evaluating. These technologies aren’t coming next year or the year after — all of the tech in question would be introduced after 2021.
“We’re going to see major transitions,” said Holt. “The new technology will be fundamentally different. The best pure technology improvements we can make will bring improvements in power consumption but will reduce speed.”

0W is the new 1GHz

It’s strange to hear Intel, which spent decades boosting computer performance, talk instead about how it will integrate new technologies to build lower-power circuits, but it’s hard to fault the firm’s reasoning. Fifteen years ago, the computer industry was focused on giving users more performance to perform more advanced tasks. Today, discussions of doing more focus on battery life, interconnected devices, the Internet of Things, and the cloud. The old paradigm was a computer that could render, retrieve, or calculate data more quickly — the new paradigm is a system that accurately retrieves your calendar, communicates with your workout sensors, or handles your scheduling.
The race between Intel and AMD to 1GHz was heralded as a triumph for Moore’s Law and the computer industry as a whole. 0W, of course, is different — computing will always costsome amount of energy — but one of the graphs from Holt’s talk illustrates Intel’s goals nicely.
In this graph, courtesy of EETimes, we see multiple technology types mapped out both in terms of absolute speed and power consumption. Our current technology is the green line. The goal is to move us farther down the y-axis through the adoption of quantum wells, spintronics, or other types of cutting-edge designs.
Unfortunately, all of the technologies that can accomplish this are orders of magnitude slower than the ones we use today. The argument Holt and others are making is that by vastly increasing power efficiency, we can compensate for decreased clock speeds, in at least many devices. This has particular relevance for exascale computing, where the power requirements of high-density parts dominates the equation and makes it virtually impossible to assemble hardware of sufficient density to create an exascale system.
“Particularly as we look at the Internet of things, the focus will move from speed improvements to dramatic reductions in power,” Holt said. “Power is a problem across the computing spectrum. The carbon footprint of data centers operated by Google, Amazon, Facebook, and other companies is growing at an alarming rate. And the chips needed to connect many more household, commercial, and industrial objects from toasters to cars to the Internet will need to draw as little power as possible to be viable.”
Intel has recently stated that it intends to compete aggressively in the Internet of Things space, but has offered little insight into what these goals for its future products mean for environments that depend on high-end CPUs. The company isn’t abandoning silicon — it envisions islands of additional capability embedded in SoCs or other types of circuits — but its move to purchase Altera and its FPGA business could reflect long-term plans for the future of traditional semiconductor performance. If traditional CPU designs can’t provide additional clock speeds and next-generation technologies are aimed at lower-power computing as opposed to higher performance, than either we’re headed for a revolution in distributed computing (unlikely), or a very, very slow performance ramp.

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